數(shù)字后端team lead
面議
5年以上
碩士
5年以上
碩士
- 全勤獎(jiǎng)
- 節(jié)日福利
- 不加班
- 周末雙休
- 領(lǐng)導(dǎo)好技能培訓(xùn)崗位晉升
2025-08-30 21:59:22
3335人關(guān)注
職位描述
該職位還未進(jìn)行加V認(rèn)證，請(qǐng)仔細(xì)了解后再進(jìn)行投遞！
職位描述：
responsibilities:
1. responsible for technical management for team and leading team to finish be tasks.
2. work as technical expert to support technical team.
3. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.
4. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).
6. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. static timing analysis (prime time) and setup/hold fix.
8. formal verification for equivalence checking (formality).
9. generation of fill structures according to technology requirements.
requirements:
1. 1-3 years experience for technical team leadership.
2. about 5 years experience in backend design flow (apr) with proven soc tape-out experience.
3. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.
4. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.
5. experience and knowledge about fe design (rtl code, flow) and verification is a plus.
6. good communication in teamwork spirit.
7. good analytical and debugging skills.
8. good command of english.
responsibilities:
1. responsible for technical management for team and leading team to finish be tasks.
2. work as technical expert to support technical team.
3. responsible for developing digital designs with emphasis on backend, including floor-plan, power planning, place, cts and route.
4. work with front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5. optimization and verification of layout for tape-out (including rc extraction, eco, drc, lvs).
6. power ir drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7. static timing analysis (prime time) and setup/hold fix.
8. formal verification for equivalence checking (formality).
9. generation of fill structures according to technology requirements.
requirements:
1. 1-3 years experience for technical team leadership.
2. about 5 years experience in backend design flow (apr) with proven soc tape-out experience.
3. experienced in synopsys/cadence automatically physical implementation tools and flows (ic-compiler/ astro / soc-encounter/ milky-way/ star-rcx) is a plus.
4. experience with one or more scripting languages (perl, tcl, or shell) to make reusable automatically flow is a plus.
5. experience and knowledge about fe design (rtl code, flow) and verification is a plus.
6. good communication in teamwork spirit.
7. good analytical and debugging skills.
8. good command of english.
注：聯(lián)系我時(shí)，請(qǐng)說(shuō)是在辛集人才網(wǎng)上看到的。
工作地點(diǎn)
地址：西安雁塔區(qū)西安-科技二路
求職提示：用人單位發(fā)布虛假招聘信息，或以任何名義向求職者收取財(cái)物（如體檢費(fèi)、置裝費(fèi)、押金、服裝費(fèi)、培訓(xùn)費(fèi)、身份證、畢業(yè)證等），均涉嫌違法，請(qǐng)求職者務(wù)必提高警惕。
職位發(fā)布者
HR
西安紫光國(guó)芯半導(dǎo)體有限公司
-
電子技術(shù)·半導(dǎo)體·集成電路
-
200-499人
-
公司性質(zhì)未知
-
陜西省西安市高新6路38號(hào)騰飛創(chuàng)新中心a座4層
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